Torrellas group contributes three articles to ISCA, selected for Retrospective of ISCA 1996-2020

Josep Torrellas
Josep Torrellas

As cloud computing becomes more popular, concerns like energy efficiency are coming to the fore. Illinois computer science professor Josep Torrellas wants to make computer deployment as efficient as possible.

Torrellas’ research team contributed three papers proposing more efficient computing architecture and hardware to the 2023 International Computer Architecture Symposium. One of the most prestigious and competitive computer science conferences, this year it was accepted just over 20% of the 372 documents presented.

Torrellas noted that his group’s papers represent work completed in the ACE Center for Evolvable Computing.

“The center is working with industry partners to come up with more energy-efficient distributed computing systems,” he said. “Not only processors, but also memories and networks. It has been very rewarding to work on something that will have such an impact on the industry.”

The first paper, “μManycore: A Cloud-Native CPU for Tail at Scale,” introduces a multicore processor design that will accelerate microservices workloads. Such workloads are common in cloud computing and website access, according to Torrellas.

“When you go to book a hotel on the web, for example, the interactions you have are based on little activities called microservices,” he said. “You choose the location where you want to find a hotel. You set the price range. Then you make your reservation, confirm it and pay. Each of these activities is a microservice.”

In this environment, while most microservices are fast, a small number of inefficient microservices throttle the entire application. Torrellas’ group proposed the μManycore processor architecture designed to mitigate this phenomenon, called “queue latency”. Unlike standard processors designed to minimize average processing time across all tasks, the new architecture optimizes what Torrellas called “hotspots” where microservices can potentially slow down, increasing queue latency.

The second paper, “MXFaaS: Resource Sharing in Serverless Environments for Parallelism and Efficiency,” presents a framework for efficiently implementing serverless environments commonly provided by cloud computing platforms, according to Torrellas.

“Serverless means the cloud gives you everything you need to run your program, and you don’t have to worry about providing libraries and other supporting code,” he said. “In this environment, programmers call the same program many times to take advantage of parallelism. With each invocation, new resources must be assigned.

With MXFaaS, researchers have demonstrated that it is possible to safely combine the resources needed for different invocations of the same program. This results in highly energy efficient execution.

The final paper, “SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM,” presents a design for specialized computing hardware, or “accelerator,” tailored for sparse matrix multiplications. These calculations are common in machine learning applications, but are inefficient on standard hardware because they require many memory accesses. These accesses waste time and energy on the computer.

SPADE is a hardware accelerator designed to efficiently perform these types of demanding operations. To demonstrate their concept, the group built a small chip for such an accelerator.

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This year, the ISCA conference celebrates its 50th anniversary. As part of the celebrations, a judging panel selected the most impactful papers from the conference’s past 25 years, and authors were asked to write a paper retrospective. A paper that the Torrellas group presented at ISCA 2006, “Bulk Disambiguation of Speculative Threads in Multiprocessors”, has been selected for the collection “Retrospective of ISCA 1996-2020”.

Their selected paper presents a scheme for improving speculative processing in parallel computing. “The idea of ​​speculation is to do more work than is needed right now,” according to Torrellas. “You may have to throw that work away later, but it could also prove very useful and advance the calculation.

“If you do this speculative work in parallel, there’s an added layer of complexity. As each processor executes part of the program, it has to check that it hasn’t stepped on each other: that is, that it hasn’t accessed the same memory locations. This is a time consuming process if done manually. Our solution was to have each processor generate, in the hardware, a summary of the memory locations it accessed. This information is stored in a “signature”. So instead of manually comparing the locations accessed by different processors to make sure they’re different, we can simply check if their signatures overlap.”

Torrellas noted that their technique was influential to the multiprocessing architectures of the time and formed the basis of some patents filed by major manufacturers

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Image Source : cs.illinois.edu

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